The company appears well positioned to challenge CPU incumbents with high performance RISC-V CPUs and Vector Extensions to the open ISA architecture. The RISC-V CPU Instruction Set Architecture (ISA) ...
ClearSpeed Technology, a provider of low-power chip-based systems, has unveiled the CS301 processor, a multithreaded chip designed to improve performance and reduce power consumption for ...
A technical paper titled “Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications” was published by researchers at Barcelona Supercomputing Center ...
Intel disclosed new technical details about its next-generation Xeon Phi processor to a small group of technology analysts-journalists at one of its Hillsboro sites this week. First revealed last year ...
If the ARM processor in its many incarnations is to take on the reigning Xeon champ in the datacenter and the born again Power processor that is also trying to knock Xeons from the throne, it is going ...
The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized ...
The ARM9-based LTC3180 combines 208-MHz, 228-MIPS performance with fine-tuned power control. Rule number one for designers of portables: Optimize the power usage in embedded applications for long ...
The introduction of complex communications protocols based on Orthogonal Frequency Division Multiplexing (OFDM) has brought with it a growing demand for high-speed Fast Fourier Transform (FFT) ...
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