New research paper titled “Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification” from researchers at University of Bristol and Infineon Technologies. “Constrained ...

Functional verification of large SoC/ASIC designs has always been a catch-22 situation. How does the verification engineer decide that enough simulations have been run on a functional block or full ...

There are three aspects to verification. As an industry, how we balance these aspects has led to a quality crisis, wrapped in a debug loop, inside a constrained random test. It’s time for a ...